At our second Bristol RISC-V Meetup last Tuesday, a packed room of 70 delegates joined UltraSoC and Imperas Software, to discuss the latest updates on the RISC-V architecture and ecosystem.
The engaging presentations at the Meetup covered a wide range of topics, including security, compliance, and code size optimization. UltraSoC CTO Gadge Panesar provided a ‘state-of-the-nation’ update from the RISC-V Foundation, as well as addressing some of the issues of systemic complexity posed by today’s large, heterogeneous SoC designs.
This was followed by a wide-ranging presentation from Imperas CEO Simon Davidmann who provided an update on compliance, progress on vector and bit manipulation instructions within RISC-V, and outlined a flow for designing new instructions.
Dave McEwan, of the University of Bristol (UoB), explained his progress in using statistical, logical, and machine learning methods to gain insights into the operation of complex chips, based on data obtained from on-chip hardware monitoring systems. Then Ben Marshall, also of UoB, outlined the challenges involved in using RISC-V for cryptographic workloads, and put forward an alternative to the standard RISC-V crypto extensions, an ISE dubbed XCrypto. More details are available here: github.com/scarv/xcrypto.
During the networking session, over light refreshments, Imperas and UltraSoC gave live technical demonstrations which generated lots of interest and good discussions.
If you would like a copy of the slides presented during the RISC-V Meetup, please email me – firstname.lastname@example.org.
We will be hosting another RISC-V Meetup in Bristol in the coming months so please sign up to the Bristol RISC-V Meetup group to be kept updated. In the meantime, our next RISC-V Meetup is taking place in Cambridge on 19th June, at Westminster College. Please click here to find out more and to book your free place. We look forward to seeing you at one of our future Meetup events!
Also check out our short highlights video here.