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UltraSoC provides a modular semiconductor IP platform that allows chip development teams to create capable, highly flexible on-chip monitoring and analytics infrastructures. These can be used both as a part of an SoC’s inherent functionality, and as a development tool that dramatically accelerates and de-risks the entire process of producing a chip.

Our IP is non-intrusive and works at wire speed. It can monitor and control chips that incorporate multiple, heterogeneous functional units sourced from many different third party suppliers, as well as custom logic designed in-house. It uses a message-based architecture, and can monitor a wide variety of system and processor events, memory interface efficiency and state machine performance. We directly support a wide variety of CPU/GPU architectures, including ARM, MIPS, Cadence Tensilica and CEVA.

Licensees have already taped-out devices at 40nm, 28nm, 16nm and 7nm process nodes.

Our IP is delivered as parameterized soft cores, allowing capabilities to be balanced against gate count according to the needs of the application on a per-instance basis. The architecture includes three classes of modules: Advanced, Message and Communicators.

Advanced modules are probes that can be integrated into the system; for example, by connecting to the block-level interfaces of system components such as bus fabric links. These are non-intrusive and ‘smart’, reporting on status without affecting performance, and delivering rich information from the stream of raw data. Message modules can be used to build a bit-width-configurable message-passing fabric independent of the system interconnect. Finally, communicator modules are used to interface UltraSoC components to external debug and performance monitoring tools.

More details on specific UltraSoC IP modules are available here.

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