RISC-V debug solutions

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RISC-V is a new open source instruction set architecture, initially developed by UC Berkeley but now being more widely adopted.

As a member of the RISC-V Foundation, UltraSoC is deeply involved in developing and defining the debug architecture for RISC-V standards. UltraSoC fully supports both standards-based and proprietary debug approaches. We were the first company to offer a RISC-V processor trace solution, supporting both open source and commercial processors including those from Andes, Codasip, Microchip, Roa Logic, SiFive and Syntacore.

Presentation: Processor Trace in a Holistic World

UltraSoC CTO Gajinder Panesar’s presentation at the 8th RISC-V Workshop in Barcelona outlined the importance of being able to debug in a holistic manner; to make the move to RISC-V as seamless as possible there needs to be an eco-system beyond the core itself.

Click to watch and you can also download the presentation via our Resources area.

“Esperanto’s goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications,” said Dave Ditzel, Founder and CEO of Esperanto. “UltraSoC’s IP will help our users see complex interactions between processors so they can understand what is going on and how to optimize performance better. Developing and debugging software utilizing thousands of RISC-V cores will be easier with the advanced analytics that UltraSoC’s IP will provide.”
Dave Ditzel

Founder and CEO, Esperanto Technologies

“The N25 and NX25 AndesCore processors are selected by our customers for their exceptional performance/power, flexible configurations, and comprehensive development tools. Choosing UltraSoC as our preferred partner for embedded analytics, trace and validation gives our customers an advanced development environment with insight into SoC operations and processor execution without disturbing target behaviour.
UltraSoC has shown itself to be committed to the development of the RISC-V ecosystem and hence it is clearly the best partner for our V5 RISC-V architecture. We are delighted to already be engaged with multiple mutual customers using Andes processor N25/NX25 with UltraSoC’s IP and trace solution to address their demanding applications.”
Charlie Su

CTO and Senior VP, Andes Technology

Click here to download the RISC-V brochure

Click below to watch the RISC-V Demo

We are also helping to define, and will fully support, the emerging processor trace specification. In many SoC solutions, customers use UltraSoC for its sophisticated system level solutions, giving rich information for complex devices with multiple cores. However, UltraSoC’s architecture is equally applicable for simpler devices, such as cost-sensitive uni-processor IoT systems. In these applications UltraSoC can simply implement standards compliant run-control and JTAG, together with a fully supported IDE.

Developing and supporting RISC-V debug standards

UltraSoC fully supports all of the major standards – both established and emerging – for RISC-V debug. And because we can monitor all major CPUs and custom logic, and perform protocol-aware probing of common buses, you can be certain that we can support you, and free you to make the best design choices for your SoC design. You can read more about our RISC-V solutions by downloading our product brief. For more information on RISC-V in general, including a presentation on debug by our CTO Gadge Panesar, visit the proceedings page of the 5th RISC-V workshop, which took place at Google’s Quad Campus in Mountain View, California.

“UltraSoC continues to prove itself invaluable in helping Microsemi cement our leadership position in SoC development.
We’re committed to providing a complete solution for development teams looking to leverage the RISC-V architecture, in a broad range of applications. Working with UltraSoC reinforces and tangibly demonstrates that commitment to our customers.”
Alan Nakamoto

Vice president, Engineering Services, Microsemi


RISC-V Foundation Event Series

UltraSoC is pleased to support and participate in the RISC-V Foundation event series.


RISC-V Summit

We were pleased to be silver sponsors of the first RISC-V Summit in Santa Clara (Dec 3-6). We demonstrated the industry’s only commercial debug and trace solution for RISC-V – as well as showed exciting developments that bring the potential of the RISC-V architecture to automotive designers.

As part of our growing involvement in the automotive functional safety and security sector, UltraSoC CTO Gajinder Panesar presented with ResilTech Senior Safety Engineer Marco Demi on ‘Functional Safety and Security, ISO26262 and their Implications for the RISC-V Ecosystem’.

On the same day, Gajinder also presented on ‘Embracing a System-Level Approach in the Real World: Combining Arm and RISC-V in a Heterogeneous Designs’.

Please click here to read his blog post ‘Systemic complexity: time for RISC-V to rise to the challenge’.

9th RISC-V Workshop

We were pleased to sponsor the 9th RISC-V Workshop which took place in Chennai, India, on 18th & 19th July 2018.
Gajinder Panesar, UltraSoC CTO, presented during the event on It’s not about the core: It’s about the system‘.

8th RISC-V Workshop

The 8th RISC-V Workshop took place in Barcelona from 7th to 10th May 2018. This Workshop was co-hosted by Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC), and sponsored by NXP and Western Digital, and showcased the significant progress the Foundation and its members have made in establishing the ecosystem for the open source processor architecture, as well as agreeing the continued evolution of its instruction set.

Please click here to watch Rick O’Connor, RISC-V Foundation Executive Director, give an introduction about RISC-V at the start of the Workshop.

UltraSoC continues to plays a leading role in the ecosystem for RISC-V, where it has become the industry standard for trace and debug. Please click here to see our blog post ‘RISC-V Workshop: security, scalability and Super Mario’.

You can also find the presentation slides from the 8th RISC-V Workshop by clicking here.

Embedded World 2018

On the RISC-V Pavilion at Embedded World 2018, which took place in Nuremberg from 27th February to 1st March 2018, UltraSoC was very busy talking with delegates about our deep involvement in developing and defining the debug architecture for RISC-V standards.

That involvement includes the UltraSoC and Lauterbach’s recent announcement about our extended collaboratively delivered universal SoC (system on chip) development and debug environment with the addition of support for the RISC-V open-source processor architecture.

On the opening morning of the show there was a full day RISC-V track, and UltraSoC CEO Rupert Baines and Russ Klein of Mentor Graphics gave a presentation on: ‘RISC-V: Emulation and Rich, Non-Intrusive Analytics Address Verification Complexity’ that explained how embedded analytics can be combined with advanced emulation technology such as Mentor’s VELOCE, to provide a development flow that combines the previously disparate pre- and post-silicon domains.

Click below to hear UltraSoC CEO Rupert Baines report from the show

Download link to UltraSoC/Mentor presentation

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RISC-V: Are we there yet…?

…there’s a chasm, and more work is needed to bridge it

An insightful blog by UltraSoC CEO Rupert Baines. With any new technology, and particular with an open standard, the question of ‘are we there yet’ will always arise. And, of course, many never go anywhere.

Remember Bluetooth? It so far outstripped expectations, that it was difficult to tell which way it was heading; but today, its success and its huge growth and industry adoption cannot be questioned… hindsight is great, isn’t it?

Click to read more

“The use of heterogeneous architectures is growing rapidly, and the rise of RISC-V shows that more than ever, designers don’t want to be restricted in their architectural choices.
Our existing relationship with UltraSoC demonstrates the power of combining our respective sets of vendor-independent development tools – giving our customers the ability to choose both the IP they use in their chip, and the environment in which they develop and debug.”
Stephan Lauterbach

General Manager, Lauterbach

“SiFive was founded with the mission to disrupt the semiconductor industry by leveling the playing field for anyone who wants to develop custom silicon.
The DesignShare ecosystem enables aspiring system designers with the tools they need when designing their SoC. We’re thrilled to welcome UltraSoC to the DesignShare ecosystem and look forward to seeing the innovations our collaboration brings to the market.”
Naveed Sherwani

CEO, SiFive