RISC-V debug solutions

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RISC-V is a new open source instruction set architecture, initially developed by UC Berkeley but now being more widely adopted. As a member of the RISC-V Foundation, UltraSoC is a leading player in defining and implementing the debug architecture for RISC V standards.

Our RISC-V debug solution scales to suit any requirement. If you’re developing a cost-sensitive uni-processor chip – for an IoT application, for example – you can use our IP to implement straightforward standards-compliant run-control and JTAG connectivity, supported by our Eclipse-based IDE. At the other end of the complexity spectrum, you can choose a system capable of delivering wire-speed trace and rich information about the operation of even the largest system-level SoC, with multiple CPUs.


Developing and supporting RISC-V debug standards

UltraSoC fully supports all of the major standards – both established and emerging – for RISC-V debug. And because we can monitor all major CPUs and custom logic, and perform protocol-aware probing of common buses, you can be certain that we can support you, and free you to make the best design choices for your SoC design.

You can read more about our RISC-V solutions by downloading our product brief. For more information on RISC-V in general, including a presentation on debug by our CTO Gadge Panesar, visit the proceedings page of the 5th RISC-V workshop, which took place recently at Google’s Quad Campus in Mountain View, California.

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