RISC-V debug solutions

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RISC-V is a new open source instruction set architecture, initially developed by UC Berkeley but now being more widely adopted.

As a member of the RISC-V Foundation, UltraSoC is deeply involved in developing and defining the debug architecture for RISC-V standards. UltraSoC fully supports both standards-based and proprietary debug approaches. We were the first company to offer a RISC-V processor trace solution, supporting both open source and commercial processors including those from Andes, Codasip, Microsemi, Roa Logic, SiFive and Syntacore.

Click here to download the RISC-V brochure

Click below to watch the RISC-V Demo

We are also helping to define, and will fully support, the emerging processor trace specification. In many SoC solutions, customers use UltraSoC for its sophisticated system level solutions, giving rich information for complex devices with multiple cores. However, UltraSoC’s architecture is equally applicable for simpler devices, such as cost-sensitive uni-processor IoT systems. In these applications UltraSoC can simply implement standards compliant run-control and JTAG, together with a fully supported IDE.


Developing and supporting RISC-V debug standards

UltraSoC fully supports all of the major standards – both established and emerging – for RISC-V debug. And because we can monitor all major CPUs and custom logic, and perform protocol-aware probing of common buses, you can be certain that we can support you, and free you to make the best design choices for your SoC design. You can read more about our RISC-V solutions by downloading our product brief. For more information on RISC-V in general, including a presentation on debug by our CTO Gadge Panesar, visit the proceedings page of the 5th RISC-V workshop, which took place at Google’s Quad Campus in Mountain View, California.

RISC-V Foundation Event Series

UltraSoC is pleased to support and participate in the RISC-V Foundation event series.

On the RISC-V Pavilion at Embedded World 2018, which took place in Nuremberg from 27th February to 1st March 2018, UltraSoC was very busy talking with delegates about our deep involvement in developing and defining the debug architecture for RISC-V standards.

That involvement includes the UltraSoC and Lauterbach’s recent announcement about our extended collaboratively delivered universal SoC (system on chip) development and debug environment with the addition of support for the RISC-V open-source processor architecture.

On the opening morning of the show there was a full day RISC-V track, and UltraSoC CEO Rupert Baines and Russ Klein of Mentor Graphics gave a presentation on: ‘RISC-V: Emulation and Rich, Non-Intrusive Analytics Address Verification Complexity’ that explained how embedded analytics can be combined with advanced emulation technology such as Mentor’s VELOCE, to provide a development flow that combines the previously disparate pre- and post-silicon domains.

Click below to hear UltraSoC CEO Rupert Baines report from the show

Find out more about RISC-V

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