UltraSoC participated in the 8th RISC-V workshop in Barcelona last week, which was a great success. It was fascinating to hear just how much, and how quickly, progress is being made by the RISC-V community. There were a few hundred attendees, ranging from big business, start-ups, through academia to hobbyists.
As sponsors of the event, and arriving in force with six staffers including our CEO, CTO, sales and engineering representatives, UltraSoC certainly made an impression. This reflects our commitment to and belief in the importance of the emerging RISC-V ecosystem.
A combination of our leading role in the RISC-V Debug Working Group, plus a barnstorming explanation of the benefits of UltraSoC’s technology by CTO Gajinder Panesar, ensured there was no shortage of interest around the technology demo at our booth. It wasn’t lost on the attendees that UltraSoC are the only company offering a RISC-V trace solution at this point in time, and our demos of run-control and instruction trace with SiFive and Andes cores attracted queues.
Western Digital were leading the charge, with an ambition to embed RISC-V cores in all of their products, more closely coupling storage and processors with a view to big data and fast processing applications.
Several groups have brought up RISC-V based systems running various Linux flavours. The RISC-V desktop PC is now a reality, including multi-core systems. Of course, being engineers, some of the first programs up and running were Doom and a Mario Kart clone…
Security was a big theme, with the words ‘meltdown’ and ‘spectre’ being thrown around liberally. There was a general feeling that an open, auditable architecture (with no previous baggage) will be very appealing to security-conscious users… the same users who might want to make use of UltraSoC’s bare-metal security offerings.
Another interesting outcome was the sheer variety of scale over which RISC-V is already being employed. Discussions ranged from huge chips containing thousands of cores, down to an IBM group talking about the production and testing of a tiny 0.3 x 0.25mm RISC-V SoC. A working group for 128-bit addressing is also taking shape, and looks to be a another potentially exciting prospect in the RISC-V world.
You can find the presentation slides from the 8th RISC-V Workshop at https://riscv.org/2018/05/risc-v-workshop-in-barcelona-proceedings