Last week I attended the very stimulating and illuminating 4th RISC-V Workshop at the MIT campus in Boston. The event was sold out with over 250 attendees representing 63 companies and 42 universities!
If you are not aware, RISC-V (pronounced “RISK Five”) is an open-source CPU instruction set architecture (ISA) that many in the industry are touting as “the Linux of hardware”. The RISC-V effort began in the Computer Science Division of the EECS Department at the University of California, Berkeley. The ISA was originally designed to support computer architecture research and education. Now, under the auspices of the RISC-V Foundation, there are moves to offer it to commercial organizations as a standard open CPU architecture.
The line-up of speakers was impressive to say the least, with plenty of contributions from heavyweight academic institutions including MIT, UC Berkeley and Cambridge University. Equally impressive is the number of commercial organizations which are already implementing, sponsoring, or evaluating RISC-V including: AMD, BAE Systems, Draper Labs, Google, HP-Enterprise, IDT, Lattice, Mellanox, Microsemi, Microsoft, NVidia, Oracle, Qualcomm, Rambus, SiFive, and Western Digital.
Needless to say, one of the big benefits of attending an event like this is the ability to have conversations during breaks and during the informal evening sessions which took place at Google’s Boston facility. Of their nature it would be wrong of me to go into detail about the content of those conversations here, but suffice it to say that I heard quite enough to convince me that there is a real prospect that RISC-V will prove to be a very disruptive force in our industry.
You might ask why a company like UltraSoC should take an interest in an open-source community like RISC-V. Well, first, it seems to me that our ambition to provide the developer community with a vendor-neutral, universal SoC development and debug flow has much in common with the aims and ambitions of the RISC-V community. We believe that developers should have a variety of tools and methodologies to choose from, irrespective of their choice of processor.
Second, and very simply, the RISC-V community is going to need to build an ecosystem of development tools. The major EDA vendors are not yet engaged, and more than one speaker highlighted the current lack of debug tools.
We think RISC-V is an exciting development, and a healthy challenge to the current hegemony of processor architectures. We will be making related announcements over the coming weeks and months, but in the meantime, we are interested in hearing your opinions about the tradeoffs and challenges associated with RISC-V and SoC debug. Please feel free to contribute to the discussion below.
If you would like to hear more about UltraSoC debug IP or discuss RISC-V, you can email me by filling in our online contact form. I look forward to attending and seeing some of you at the 5th RISC-V conference scheduled for November at the Google campus in Mountain View, CA.