Patterson_RISC-V_2018_keynoteThe first RISC-V Summit, which took place in Santa Clara, CA early this month, looks likely to be a watershed for the RISC-V ecosystem.

The technology is maturing and the ecosystem is growing fast – and that was reflected in the nature of the presentations and news announcements we saw. The accent has started to move to how the technology will be used in real life: UltraSoC’s announcement of a hardware-based lockstep solution for automotive applications being a good example. RISC-V lacks native support for lockstep, which is strongly recommended for designs with a functional safety dimension.

RISC-V will take its place alongside other processor architectures:
notably Arm

Meanwhile at the conference, our CTO Gajinder Panesar continued to encourage ecosystem members to take a more system-level approach, as well as pushing forward the ISA and core design dimensions. Gadge argues that RISC-V will take its place alongside a raft of other processor architectures – most notably Arm. So developing an ecosystem that can support heterogeneous designs – those that include cores built with different base architectures – is vital.

As well as the systemic complexity involved in such designs, Gadge identifies a number of factors – including the trend towards systems that are not “architected” in the traditional sense, ad-hoc programming models and the use of NoCs – which need to be addressed. You can read more in his blog post here.

Looking further afield, one of the big news items was Western Digital’s announcement of its RISC-V SweRV Core™, OmniXtend on-chip interconnect architecture, and supporting instruction set simulator. It’s not the first time WD has made a splash at a RISC-V event. This time last year it announced that it will be transitioning all of its CPU usage to RISC-V: it’s great to see the company delivering such concrete progress towards this commitment.

Many other RISC-V Foundation members made major announcements, including Microsemi, which unveiled its new PolarFire SoC architecture, described by Bruce Weyer, vice president of the company’s Programmable Solutions BU, as “a compelling combination of low power, security and reliability in a configurable device that brings real-time to Linux.”

At more than double the size of the corresponding event in 2017, the RISC-V Summit bore testament to the rapid growth of the ecosystem. But there is more to do, particularly in Europe where adoption and awareness is lagging behind that in North America and the Far East….  to which end, the next major RISC-V event is scheduled for February’s Embedded World show in Nuremberg, where the Foundation will have a pavilion that will feature UltraSoC and many other member companies, including Andes, CloudBEAR, Greenwaves, Imperas, SiFive and Syntacore. We look forward to seeing you there.