I’m back in San Jose for the second time in just a couple of months, it’s been interesting to compare the two events I’ve attended here recently – Arm Techcon and the 2019 RISC-V Summit.

 

 

The worlds of RISC-V and Arm have often in the last couple of years tried to pretend that they’re hermetically sealed, separate environments. But increasingly, it’s becoming clear that nothing could be further from the truth.

At UltraSoC we’ve been aware for some time that the future is heterogeneous. For RISC-V, that means coexisting with, rather than replacing, Arm, and taking a more holistic, system-level view of the ecosystem.

And after this year’s TechCon, it seems that ‘heterogeneous’ will also be taking on a new meaning. For a long time, the techie in-joke was that for Arm, ‘heterogeneous computing’ meant a chip with an M3 and A9 on the same die (for those not in the know, the M3 and A9 are both Arm processors). But the big news back in October was Arm’s announcement that it is opening up its instruction set so that people can add custom instructions.

Of course, this mimics one of the great strengths of RISC-V – a standardized instruction set but one on which people can build, add value and innovate.

This kind of approach fosters diversity; but at the risk of fragmentation. One of Arm’s great strengths to date has been that if two vendors’ chips use the same CPU core, you can be pretty certain they’ll execute the same code. That could change as vendors start to add their own instructions.

RISC-V is in a similar situation: how do you balance the need to create a healthy, diverse ecosystem, acknowledge that ‘one size doesn’t fit all’, while avoiding fragmentation and confusion. The RISC-V Foundation is already making moves to ensure that balance is better served in the future, having announced that it will recruit a technology leader to work with community members to facilitate the Foundation’s technical vision and cultivate stakeholder engagement.

Fostering the ecosystem is the prime motivation behind our announcement at the Summit that we’ll be producing an open-source trace encoder, based on the work going on in the processor trace group of the RISC-V Foundation. We’ll be doing this through the OpenHW Group, which had its own news announcement at the show, disclosing an aggressive timescale for taping out a heterogeneous (there’s that word again!!) multi-core processor evaluation SoC, capable of running the Linux operating system, during the second half of 2020.

Elsewhere during the RISC-V conference sessions, our CTO Gadge Panesar presented more details of our approach to cycle-accurate tracing – a key technology for real-time and high-performance systems.