Last week I attended the inaugural Indian RISC-V Workshop in Chennai, hosted by the Indian Institute of Technology Madras (IIT).

For myself and my colleague, UltraSoC CTO Gajinder Panesar, our goals were to understand more about the state of the Indian semiconductor market and to connect with partners and prospects, as well as enjoying the culture and eating some great Indian food. We managed to tick all those boxes, and more!

There was an energy and excitement in the air at the event, a sense of a community on the cusp of something big, something important, a spirit of collaboration as we build something new together. The Indian government has strongly endorsed the RISC-V standard, which is being embraced not only in the Indian academic world but also the governmental technology units (defense, space etc.) and the rapidly growing local semiconductor industry which boasts a healthy design service sector and a vibrant start-up community with particular emphasis on the IoT space.

For me there were three key themes at the event: Data, Ecosystem and Business Models.

Listening to the Western Digital keynote speech, I was particularly struck by their differentiation between Big Data and Fast Data. UltraSoC IP certainly has the capability to produce Big Data. Our RISC-V trace encoder is first to market and already yielding results for our customers who post-process the large quantities of data produced to improve quality and reduce time to market. Gadge demonstrated this to a large audience during the event, showing our powerful ability to deal with heterogenous SoC environments with cores from different vendors running different instruction sets (including RISC-V).

But we can also produce Fast Data. Because our monitors operate in hardware, we can detect issues in real time – for example, that someone is attempting to access a secure area of the SoC. The sign at the local bus stop at IIT Chennai does say “better late than never” but identifying security threats late, or never identifying them at all, could have catastrophic consequences. This is the kind of data that *must* be fast, the kind of “fast” that only a hardware solution can provide.

On Wednesday evening we ate an excellent, and beautifully presented, northern Indian thali dinner. Each element by itself was wonderfully tasty, but also worked in harmony with the other elements, and as a result the overall meal became more than the sum of the individual parts. This made me think about another theme of the RISC-V event – that what’s actually important is the whole system, not just the core. A lot of emphasis of the early RISC-V work has been on the instruction set for the core, and indeed we heard many presentations focused on cores during the Chennai RISC-V event.

The core is like the individual Balti dishes that make up a thali, and it’s exciting to see that these are bubbling away, nearing commercial readiness. But as we approach commercial deployment, other elements beyond the core are increasingly important. It was clear from speaking with people at the event that RISC-V will be deployed pragmatically – most designers will initially deploy RISC-V cores alongside other technologies in their SoCs rather than doing massive swap-outs. So the emergence of an ecosystem to support RISC-V in heterogeneous environments is critical. We are proud to be one of the early members of this ecosystem, and by building strong partnerships with others like Imperas our goal is that, like the thali, the end result for our customers will be more than the sum of the individual parts!

There was a fascinating panel session on Wednesday afternoon examining how RISC-V can be a game-changer for the Indian semiconductor industry. While the panel focus was on India, the concepts were applicable globally, and reminded us that creating new and innovative business models enabled by the emergence of a vibrant RISC-V ecosystem must now become a major concern.

To that end we look forward to broadening our engagement with universities beyond technology to the business, management, marketing and economics departments as we formalize our university liaison program over the coming weeks. Check back here for more details!