Kevin McDermott is VP Marketing with Imperas
We recently experienced the excitement and extent of the ‘Embedded Revival’ for new market opportunities at both the 55th Design Automation Conference (DAC) in June, in San Francisco, and the RISC-V Workshop in July in Chennai, India.
The vast majority of designs today are multi-core and many-core designs. And increasingly, semiconductor and system developers, as well as embedded software developers, are aware of the competitive advantage high-level simulation and debug tools can deliver. Much of this interest is fueled by rapidly-evolving artificial intelligence (AI), machine learning (ML), IoT and other applications.
One key issue was how to address the complexities of the debug and testing process with new SoC architectures that include heterogeneous CPUs. As the Embedded Markets Survey by Aspencore (EE Times, Embedded) 2017 showed, debug is the most significant challenge:
But now, as we announced in June, UltraSoC, with embedded analytics, and Imperas, with virtual platforms, can provide developers of multi-core SoCs with the powerful combination of an advanced debug environment, embedded analytics, and virtual platform technologies for hardware, software, and simulation.
Click to watch an insightful, short video about Imperas / UltraSoC partnership benefits by Rupert Baines, UltraSoC CEO
Click here to watch a recent video of a paper presented by Simon Davidmann, Imperas CEO on the Common Software Debug environment.
Click link to read the UltraSoC / Imperas press release here.
And learn more at these upcoming events…
See both Imperas and UltraSoC at:
- DVCon Europe, October 24, in Munich, Germany, featuring a joint tutorial with Imperas, UltraSoC and Codasip.
- The RISC-V Summit Silicon Valley, in December 2018.
At both DAC and the Chennai RISC-V event, there was great energy around system-level design approaches, hardware-software integration and multicore architectures, and especially the fast-growing AI, ML, IoT and other applications.
It takes two!
- UltraSoC for on-chip monitoring, analytics and debug technology, via a combination of semiconductor IP and associated software.
- Imperas virtual platforms so software developers can start work at the earliest possible stage in an SoC project, with debug tools for full system behavior visibility.
The bottom line is: a powerful integrated design flow with a common software debug environment that gives a smooth transition as a project develops.