At Embedded World 2018, UltraSoC joined the RISC-V Foundation stand – Rick O’Connor from the Foundation has kindly shared his thoughts on the success of the show, testament to the significant progress of RISC-V.  UltraSoC will once again be participating at the 8th RISC-V Workshop in Barcelona on 7-10th May. If you’re going to be there, email to jo.windel@ultrasoc.com to arrange a meeting with UltraSoC.

RISC-V Foundation at Embedded World 2018

By Rick O’Connor, Executive Director, RISC-V Foundation

This year, the RISC-V Foundation had an incredible presence at Embedded World 2018. For the first time, the Foundation hosted a booth that featured member companies Antmicro, GreenWaves Technologies, Imperas, Syntacore, VectorBlox and UltraSoC co-exhibiting in the RISC-V Foundation booth. There was so much energy, excitement and interest in the Foundation and its membership, clearly showing the great momentum we’re witnessing together around the free and open RISC-V ISA.

On the first day of the show, Embedded World featured a RISC-V Class with 10 presentations with representatives from Dover Microsystems, ETH Zurich, GreenWaves Technologies, Imperas, Mentor Graphics, Microsemi, the RISC-V Foundation, Syntacore, UltraSoC, University of Bologna and University of Colorado Boulder all speaking about recent product developments using the RISC-V ISA. Each session was well attended with plenty of good questions.

We also hosted a RISC-V Foundation scavenger hunt which allowed attendees to travel the show floor and visit all RISC-V members. Across the expansive Embedded World conference center, we had participation from 14 RISC-V Foundation member companies including: Antmicro, Ashling Microsystems, Cortus, Express Logic, GreenWaves Technologies, Imperas, Lauterbach, Microsemi, SEGGER Microcontroller, Syntacore, Trinamic, UltraSoC, VectorBlox and Western Digital. Once attendees completed their hunt, they returned to the RISC-V booth and entered into a raffle for some amazing prizes (thanks to SiFive, SEGGER Microcontroller and Microsemi).

It was a very busy and fast three days and I continue to be encouraged by the overwhelming adoption of the free and open RISC-V ISA paving the way for the next 50 years of computing design and innovation.

Next up, we’ll be busy with preparations for the next RISC-V workshop. Scheduled May 7 – 10, this workshop will be co-hosted by Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC) and sponsored by NXP and Western Digital in Barcelona, Spain. We’re still seeking proposals for talks and poster presentations, see details here and please register to attend here.

Happy to chat more about the RISC-V ISA or the Foundation, please feel free to connect on Twitter (@rickoco).