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May 2020

Webinar: Multicore RISC-V Designs in AI & Machine Learning Applications

06 May 2020 @ 4:00 pm-5:00 pm

Andes, Imperas, and UltraSoC hosted a webinar on how to easily optimize (including custom instructions and Vector, DSP extensions), accurately simulate, and precisely instrument, multicore RISC-V designs for AI Inferencing or ML applications. The webinar was run twice on 6 May 2020, at 8am PDT (4pm BST, 5pm CET, 11pm CST) and 5pm PDT (1am BST, 2am CET, 8am CST on May 7). Click here to access the webinar recording The webinar covered the latest challenges’ designers are facing migrating…

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Automotive Cybersecurity Seminar – Postponed

06 May 2020

The Automotive Cybersecurity Seminar due to take place on 6th May at the MIRA Technology Institute in Nuneaton, UK, has been postponed, given the current coronavirus situation. We will update this event once we know more. Vehicles and their systems have certainly been hacked in trials and demonstrations – though not to any significant degree in real-life situations – at least so far as we know. The technical talks will centre on Raising awareness of the importance and relevance of cybersecurity to…

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April 2020

Webinar: Insights beyond the core: the power of embedded analytics

30 April 2020 @ 3:30 pm-4:45 pm

UltraSoC CSO Aileen Ryan and CTO Gajinder Panesar provided a whistle-stop tour demonstrating the power of hardware-based monitoring and analytics in the product development flow. Delegates joined the webinar on 30 April 2020 to learn about UltraSoC's embedded analytics technology and how we are ensuring systems do what they are designed to do... safely and securely. Access the webinar recording here. The webinar covered: How hardware-based analytics benefits the entire product lifecycle, from architectural exploration, through implementation, to in-field optimization,…

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RISC-V Service Tools Virtual Meetup

23 April 2020 @ 4:00 pm-5:30 pm

Join us for the 2nd RISC-V meetup in Israel, hosted by Western Digital, UltraSoC and Codasip, to discuss RISC-V debug & trace infrastructure, unique paging techniques and SweRV Core™ support. The online event will be held on Thursday, April 23rd, 2020, 6:00pm-7:30pm Israel Day Time. 5:45-6:00 - Login & hello 6:00-6:25 - Debug and Trace Infrastructure for RISC-V SoC, UltraSoC 6:25-6:50 - Enabling the commercial deployment of SweRV Core™, Codasip 6:50-7:15 - ComRV, Cacheable Overlay Manager for RISC-V, Western Digital…

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March 2020

Accelerating AI through hardware – postponed

31 March 2020

The 'Accelerating AI through hardware' event has been postponed, given the current coronavirus situation. UltraSoC CSO Aileen Ryan will participate in this event at Bristol University when it has a confirmed new date.  We will update this event page once we know more. Artificial Intelligence now impacts every aspect of modern life, not least in the sphere of business. AI, Neural Networks or Machine Learning technologies are rapidly being adopted and applied across a range of products and systems, trying to further increase…

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