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Western Digital: RISC-V SweRV Core Deep Dive

21 February 2019 @ 5:30 pm-8:00 pm

UltraSoC are looking forward to participating in Western Digital’s RISC-V SweRV Core Deep Dive Meetup which is taking place on 21st February 2019 at their Milpitas offices in California.

Western Digital recently open sourced the first production grade RISC-V core, the SweRV Core EH1. At this meetup, the architecture details on this 32 bit core will be discussed. Technical experts will explain the tradeoff decisions made when developing the SweRV Core EH1, targeted applications and a technical code walk through will be shown.

Agenda:
5:30-6:30 Networking & Refreshments
6:30 SweRV Core Architecture Deep Dive
7:00 SoC Level Analytics, Trace & Debug for SweRV Core Designs

Places are filling up fast so please book soon via the Meetup event page here.

 

 

Details

Date:
21 February 2019
Time:
5:30 pm-8:00 pm
Event Tags:
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