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Webinar – RISC-V Custom Instructions for accelerators and direct multicore communications for 5G, AI, AR/VR, and IoT

29 September 2020 @ 4:00 pm-5:00 pm

Join the Andes, Imperas, and UltraSoC webinar on the flexibility of RISC-V in SoC designs with optimized extensions and custom instructions.

When: Tuesday 29th September 2020
Time:  8am PDT / 4pm BST

Register your place to attend the webinar or receive the link to view the recording later.

The webinar will start with an architectural exploration to profile applications and identify candidate instructions, then provide details of the design flow to implement and verify new extensions, followed by use of on-chip instrumentation for debug, analysis and lifecycle management.

RISC-V is opening up new aspects of design freedoms with optimized solutions beyond the boundary of standard processor core roadmaps. Domain specific optimizations offer just the right balance between hardware efficiency and software flexibility. Start exploring your next project with the flexibility of RISC-V and optimized extensions.

The webinar will conclude with a hosted Q&A session with the presenters as a group discussion.

Unable to join on the day? Please still register, and you will be sent a recording of the webinar when it is available.

Part 1 (click here to watch) of our webinar series focused on architecture

Part 2 (click here to watch) of our webinar series focused on hardware and software implementation



29 September 2020
4:00 pm-5:00 pm
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