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RISC-V Technical Symposium Moscow

20 May 2019

SiFive, the company founded by the inventors of the RISC-V architecture, and Syntacore, a founding member of the RISC-V Foundation and leader in RISC-V processor IP cores, are jointly hosting a RISC-V Technical Symposium in Moscow on Monday, May 20, 2019 at the Holiday Inn Moscow Lesnaya.

UltraSoC are looking forward to participating in the event, which will feature presentations by industry veterans, ecosystem partners and researchers from academia. Attendees will learn about custom cores and design platforms, and the SaaS-based approach that is enabling fast and easy access to them. We will also showcase currently-available RISC-V core development boards, high bandwidth memory IP subsystem validation boards and customizable RISC-V SoC platforms, all of which reduce risk, development time and cost while enabling differentiation within silicon.

This symposium is intended for engineers and electronics professionals, electronics-focused academicians, and electronics and electrical associations. Attendance is free for qualified attendees (preliminary registration required).

UltraSoC CEO Rupert Baines will be presenting on ‘SoC Level Analytics, Trace & Debug for RISC-V Designs’.

To find out more information, please visit the event website.

Details

Date:
20 May 2019
Event Tags:
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Website:
https://riscv.expert/en/