Cambridge RISC-V Meetup
19 June 2019 @ 6:00 pm-8:30 pm
Following our successful first RISC-V Meetup in Cambridge last November, we are pleased to invite you to join us at our second one on Wednesday 19th June 2019, which will take place at Westminster College, Cambridge, and will be hosted by UltraSoC and Imperas Software!
The evening will start at 6pm with a networking session, including refreshments. We will have a number of interesting speakers, and there will also be live technical demonstrations. More information will be updated here soon.
Please click here to book your place.
Places are limited, so please book soon! We look forward to seeing you there.
Please visit https://riscv.org/ for more information about RISC-V, and to read how, as a member of the RISC-V Foundation, UltraSoC is deeply involved in developing and defining the debug architecture for RISC-V standards, visit https://www.ultrasoc.com/technology-2/risc-v/. Imperas helps RISC-V developers with virtual platforms and tools for early software development, RISC-V compliance testing and test development. Visit http://www.imperas.com/imperas-riscv-solutions.
You may like to check out our blog post from our first Cambridge Meetup: ‘RISC-V in Cambridge’.
Also, if you are interested in speaking at a forthcoming RISC-V Meetup, please do get in touch by sending an email to firstname.lastname@example.org. This community is to provide an open platform for all in which to share experiences, to build understanding and open doors to opportunities based on the RISC-V architecture.