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8th RISC-V Workshop
07 May 2018-10 May 2018
UltraSoC participated in the latest (8th) RISC-V Workshop in Barcelona, 7th to 10th May 2018.
This Workshop was co-hosted by Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC), and sponsored by NXP and Western Digital, and showcased the significant progress the Foundation and its members have made in establishing the ecosystem for the open source processor architecture, as well as agreeing the continued evolution of its instruction set.
UltraSoC continues to plays a leading role in the ecosystem for RISC-V, where it has become the industry standard for trace and debug.
Monday 7th May – CTO Gajinder Panesar will be presenting in a Tutorial on ‘RISC-V Debug Spec’
Tuesday 8th May – CTO Gajinder Panesar and Simon Davidmann of Imperas will be presenting on ‘A Common Software Development Environment for Many-core RISC-V based Hardware and Virtual Platforms’
Wednesday 9th May – CTO Gajinder Panesar will be presenting on ‘Processor Trace in a Holistic World’
Thursday 10th May – CTO Gajinder Panesar, Chair of the RISC-V Processor Trace Group, and Co-Chair, Hugh Okeeffe, Ashling Microsystems: an introductory discussion session
Please click here to see our blog post ‘RISC-V Workshop: security, scalability and Super Mario’.
You can also find the presentation slides from the 8th RISC-V Workshop by clicking here.