UltraSoC and SiFive bring embedded analytics to more RISC-V applications

SiFive logoThis week, we were delighted to announce we have struck a partnership with SiFive, joining their DesignShare programme to extend the opportunities for new applications developed on the increasingly popular RISC-V open source platform. We’ll be working together to provide RISC-V processor trace and debug for the SiFive Freedom platform.

Continue reading

UltraSoC funding: Managing security and safety risks is no longer enough, intelligent control must be embedded

We are delighted to have announced last week that we closed a £5m round of funding, with a strong line-up of new and existing investors.

And now this week , Alberto Sangiovanni-Vincentelli , a co-founder of both Synopsys and Cadence, has joined our advisory board to bring us the benefits of his significant wisdom – that’s further strengthening the UltraSoC team.

Continue reading

Ensuring SoC reliability via on-chip analytics and monitoring

You may have read the news a couple of weeks ago that we’re working with Moortec Semiconductor on next-generation intelligent process, voltage and temperature (PVT) sensor systems. We’ve combined UltraSoC’s digital monitoring and optimization capabilities with Moortec’s leading PVT products to enable real improvements in SoC performance and reliability. Continue reading

Server performance problem or bug? In a world of long tail latency, sampling profilers won’t do

I just read an outstandingly interesting blog post, about how Google and others optimize the performance of their servers – and on the importance of finding subtle bugs (some of which are so subtle they don’t even qualify for the term “bug”, but nevertheless are so influential as to define the performance of an entire complex system). It’s recommended reading for anyone interested in complex systems – and for those who just want an insight into how Google works. One of those (sadly rare) things you read that give a whole new perspective. Continue reading

Codasip and UltraSoC deliver advanced RISC-V SoC analysis and debug

CAMBRIDGE, UK, and SAN JOSE, CA, 22nd November 2016

Codasip, the leading RISC-V processor IP provider, and UltraSoC, the leading provider of semiconductor IP for on-chip analytics, performance optimization and hardware-based security and debug, announced a broad collaboration to integrate the Codix-Bk series of RISC-V compliant processor cores seamlessly with the UltraSoC environment. As RISC-V based SoCs enter the mainstream, the need for commercial support with production-quality debug, analysis and bring-up tools become critical. This collaboration provides the RISC-V community with capabilities that go beyond those available to proprietary processors and instruction set architectures (ISAs). Continue reading

Building success: semiconductors, software and open source

Rupert Baines

Rupert Baines

Last month saw two major events in the electronics industry, both of which are significant for the UK for both business and technology reasons.

First (as anyone with even a passing interest in the semiconductor industry will already know) Softbank bought ARM for a reported $31M. The only global-scale technology company in the UK is now Japanese owned.

Continue reading

Still debugging the JTAG way? Time to try the USB way…

JTAG (or IEEE1149, to give it its official title) is a remarkable success story. A humble technology, originally conceived to help test printed circuit boards, it has been in practical use for around 30 years. It is deeply embedded in almost every chip design – so much so that NOT using it has become the exception rather than the rule.

And yet for all its success, JTAG really is woefully inadequate as an SoC debug interface. By modern standards, it is slow: a maximum throughput of 6Mbps doesn’t even scratch the surface of today’s designs, which boast SerDes interfaces that function at 1000x times that rate, and routinely clock at gigahertz speeds. Continue reading

RISC-V: the Linux of hardware?

Randy Fish

Last week I attended the very stimulating and illuminating 4th RISC-V Workshop at the MIT campus in Boston. The event was sold out with over 250 attendees representing 63 companies and 42 universities!

If you are not aware, RISC-V (pronounced “RISK Five”) is an open-source CPU instruction set architecture (ISA) that many in the industry are touting as “the Linux of hardware”. Continue reading

The real semiconductor crisis is post silicon (and why the CFO should care)

If you follow the semiconductor industry, you’ll have read a lot about the “semiconductor productivity crisis”: and it is a business issue, not just an engineering one.

As chips get more complex, the argument goes, they become ever harder to design: the tools available to us haven’t kept up with process technology, Moore’s Law and the increasing use (and re-use) of IP. Complexity has grown exponentially – the intelligence in the development process has not.

And this has a disproportionate impact on the cost and profitability of the business.

But is silicon design REALLY the problem? Continue reading