Here at UltraSoC we see regular evidence of the increasing traction surrounding RISC-V. Earlier this week Ann Steffora Mutschler of Semiconductor Engineering published an interesting blog post taking a look at the state of the technology and market: it’s great to get some independent recognition of what we believe ourselves – that RISC-V is now pushing into the mainstream. According to Ann:
“RISC-V is pushing further into the mainstream, showing up across a wide swath of designs and garnering support from a long and still-growing list of chipmakers, tools vendors, universities and foundries. In most cases it is being used as a complementary processor than a replacement for something else, but that could change in the future.”
Ann’s piece continues:
“RISC-V also could gain traction with proprietary architectures, given the huge investments organizations make in code and instruction sets and architectures, suggested Rupert Baines, CEO of UltraSoC. ‘Another facet to this is critical mass, and it can be very expensive and very difficult to develop support, maintain anything below that critical mass. For companies like Nvidia, which have their own completely custom thing, well now they’ve got a RISC-V. They benefit from all the tools, compilers, and it’s still their own custom thing, but they’ve just made their development costs much lower because they can leverage everything else.'”
Click here to read Ann’s article in full
You may also be interested in reading more about how, as a member of the RISC-V Foundation, UltraSoC is deeply involved in developing and defining the debug architecture for RISC-V standards. UltraSoC fully supports both standards-based and proprietary debug approaches. We were the first company to offer a RISC-V processor trace solution, supporting both open source and commercial processors including those from Andes, Codasip, Microsemi, Roa Logic, SiFive and Syntacore.
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