JTAG (or IEEE1149, to give it its official title) is a remarkable success story. A humble technology, originally conceived to help test printed circuit boards, it has been in practical use for around 30 years. It is deeply embedded in almost every chip design – so much so that NOT using it has become the exception rather than the rule.
And yet for all its success, JTAG really is woefully inadequate as an SoC debug interface. By modern standards, it is slow: a maximum throughput of 6Mbps doesn’t even scratch the surface of today’s designs, which boast SerDes interfaces that function at 1000x times that rate, and routinely clock at gigahertz speeds.
It is also costly: it’s not unusual to pay $500 for a JTAG probe. The practical result for chip design teams is often that only a handful of team members get access at any one time during chip bring up. And that obviously impacts the project schedule.
It costs pins: the JTAG interface needs to be brought out externally to facilitate interconnection.
JTAG also presents a physical problem. It’s tricky enough during the post-silicon bring-up stage, but most end systems don’t even offer access to the JTAG interface, making it difficult or impossible to understand the device’s behavior in a real-world context.
Given its drawbacks, the continuing success of JTAG is remarkable: all the more so when you consider that most modern SoCs already include a better alternative, in the shape of a USB interface. Users of UltraSoC’s IP know all about the power and flexibility of USB for debug. We provide a unique, patented technology that allows a single high-speed chip interface to be used simultaneously for both system communication and for analytics applications.
Using USB means that there is no need to rely on a debug-specific interface – developers can “look in” to a chip and analyze its behavior via an external interface that is already an intrinsic part of the SoC design. Every development team member can connect a target system to their computer using a standard USB cable and immediately become productive
Using this approach, dedicated debug I/O pins become unnecessary; data transfer can be accomplished much more quickly (at a theoretical maximum rate of up to 480Mbps using USB 2.0); and optionally, the interface remains accessible even once the chip has been assembled into an end product and shipped to the customer. This allows system designers to analyze problems and fine-tune the performance of a product throughout its useful lifetime.
The UltraSoC connectivity feature is backed with advanced security capabilities such as challenge/response authentication, cryptographic protection and the ability to completely disable the debug facility, allowing OEMs to deploy products with complete confidence.
We believe that using USB for debug represents the future, and to facilitate its uptake, we’ve now “unbundled” our USB connectivity solution so that it can be used on any SoC – not just those equipped with UltraSoC monitoring and analytics IP. Our standalone USB Communicator IP block implements a cut-down USB MAC that connects directly to a USB PHY interface (or optionally to our own USB debug hub IP). It is autonomous, requiring no host processor or software intervention. No changes are required to the main system software, and no processor cycles are ‘stolen’ from the target system. Should the data need to be serially scanned out, UltraSoC provides a block which sits behind the USB communicator. This provides the more ‘classic’ serial scan chain capability, by using the USB as the interface into the SoC.
JTAG has a long and distinguished history in SoC debug. But history is not enough: it’s time to move to the kind of debug connectivity that befits a modern SoC.