Codasip and UltraSoC deliver advanced RISC-V SoC analysis and debug

CAMBRIDGE, UK, and SAN JOSE, CA, 22nd November 2016

Codasip, the leading RISC-V processor IP provider, and UltraSoC, the leading provider of semiconductor IP for on-chip analytics, performance optimization and hardware-based security and debug, announced a broad collaboration to integrate the Codix-Bk series of RISC-V compliant processor cores seamlessly with the UltraSoC environment. As RISC-V based SoCs enter the mainstream, the need for commercial support with production-quality debug, analysis and bring-up tools become critical. This collaboration provides the RISC-V community with capabilities that go beyond those available to proprietary processors and instruction set architectures (ISAs).

While selecting a processor and ISA is one of the first challenges for engineers in architecting a new SoC, the real difficulties come when they try to bring the design to life, to productize and optimize it in the real world. While RISC-V provides an ISA for processor IP, it does not in itself solve all the other problems of support, commercialization or development. This partnership focuses on that need. Rather than simply adapt legacy solutions to the RISC-V environment, this collaboration delivers a complete solution that will not only accelerate time-to-market, but extend analysis and improvement capabilities beyond initial deployment.

“Our customers demand more than just traditional processor-based debug in order to meet the needs of the IoT era,” said Karel Masarik, CEO, Codasip. “UltraSoC’s broad range of capabilities combined with our commercially proven processor infrastructure, supported on our RISC-V series of Codix-Bk processors, drastically accelerates SoC deployment. We are excited by what this collaboration enables and the benefits it delivers to the new era of RISC-V based SoCs.”

While RISC-V is establishing itself as the choice for new SoC designs, engineers need proven development infrastructure and commercial support. This collaboration addresses both needs: Codasip provides proven processor IP and infrastructure, while UltraSoC extends this to enable a rich and versatile toolkit for debug, optimization and analytics. This collaboration is an example of how the open-source RISC-V ecosystem can innovate quickly to deliver more than is available with legacy proprietary architectures.

“RISC-V is rapidly becoming an exciting ISA choice for new designs, but suffers from the lack of a proven implementation platform,” said Rupert Baines, CEO, UltraSoC. “Combining UltraSoC IP with proven Codix-Bk IP and debug environment results in a powerful SoC debug, analysis and chip-bring up environment that will dramatically accelerate development time while reducing risk for new SoC starts.”

The combined solution is available immediately. Both companies are committed to continually evolve their solutions to conform to the RISC-V foundations specifications (riscv.org).

“RISC-V adoption continues to accelerate with ultimate success requiring the ecosystem evolve beyond initial processor specifications with a focus on the challenges of the SoC creators,” said Rick O’Connor, Executive Director of the RISC-V Foundation. “We’re excited to see Codasip and UltraSoC working together to make customers’ RISC-V based designs a reality.”

About Codasip

Codasip delivers leading-edge processor IP technology that provides the advantages of industry standard processor IP with the ability to optimize for your unique application. Codasip’s unique model-based processor IP, and application analysis technology, makes processor customization and optimization available to any design team. As a founding member of the RISC-V foundation (riscv.org) and long term supplier of LLVM and GNU based processor solutions Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe. More information on Codasip’s products and services is available at www.codasip.com.

About the RISC-V Foundation

RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.