I just read an outstandingly interesting blog post, about how Google and others optimize the performance of their servers – and on the importance of finding subtle bugs (some of which are so subtle they don’t even qualify for the term “bug”, but nevertheless are so influential as to define the performance of an entire complex system). It’s recommended reading for anyone interested in complex systems – and for those who just want an insight into how Google works. One of those (sadly rare) things you read that give a whole new perspective. Continue reading
CAMBRIDGE, UK, and SAN JOSE, CA, 22nd November 2016
Codasip, the leading RISC-V processor IP provider, and UltraSoC, the leading provider of semiconductor IP for on-chip analytics, performance optimization and hardware-based security and debug, announced a broad collaboration to integrate the Codix-Bk series of RISC-V compliant processor cores seamlessly with the UltraSoC environment. As RISC-V based SoCs enter the mainstream, the need for commercial support with production-quality debug, analysis and bring-up tools become critical. This collaboration provides the RISC-V community with capabilities that go beyond those available to proprietary processors and instruction set architectures (ISAs). Continue reading
Last month saw two major events in the electronics industry, both of which are significant for the UK for both business and technology reasons.
First (as anyone with even a passing interest in the semiconductor industry will already know) Softbank bought ARM for a reported $31M. The only global-scale technology company in the UK is now Japanese owned.
JTAG (or IEEE1149, to give it its official title) is a remarkable success story. A humble technology, originally conceived to help test printed circuit boards, it has been in practical use for around 30 years. It is deeply embedded in almost every chip design – so much so that NOT using it has become the exception rather than the rule.
And yet for all its success, JTAG really is woefully inadequate as an SoC debug interface. By modern standards, it is slow: a maximum throughput of 6Mbps doesn’t even scratch the surface of today’s designs, which boast SerDes interfaces that function at 1000x times that rate, and routinely clock at gigahertz speeds. Continue reading
Last week I attended the very stimulating and illuminating 4th RISC-V Workshop at the MIT campus in Boston. The event was sold out with over 250 attendees representing 63 companies and 42 universities!
If you are not aware, RISC-V (pronounced “RISK Five”) is an open-source CPU instruction set architecture (ISA) that many in the industry are touting as “the Linux of hardware”. Continue reading
If you follow the semiconductor industry, you’ll have read a lot about the “semiconductor productivity crisis”: and it is a business issue, not just an engineering one.
As chips get more complex, the argument goes, they become ever harder to design: the tools available to us haven’t kept up with process technology, Moore’s Law and the increasing use (and re-use) of IP. Complexity has grown exponentially – the intelligence in the development process has not.
And this has a disproportionate impact on the cost and profitability of the business.
But is silicon design REALLY the problem? Continue reading
Today’s embedded development projects are more complex than ever – but the good news is that designers have never been better supported with hardware and software tools that can help make their ideas a reality. At UltraSoC we see ourselves as very much a part of that enabling ecosystem: and that’s why we partner with providers of best-in-class development tools that can help engineers to make maximum use of our monitoring and analytics products. Continue reading
An interesting blog by Don Dingee over at SemiWiki poses the question “Should there be a five second rule for IoT chips?”
Don worries that today’s (and tomorrow’s) IoT chips may not be sufficiently well validated and tested for manufacturers to be able to confidently deploy them “anywhere”.
In Don’s view, “Allowing consumers to put these IoT chips that we just slapped together in their ‘mouths’ or other sensitive places and find out what happens is asking for trouble.”
And he’s right.
Ed Sperling’s recent excellent article about the challenges of gathering and processing data for system-level design really got me thinking.
Ed summarizes some very relevant and pithy thoughts coming from a number of different parts of our industry – including EDA vendors, design houses, and IP providers. Rightly in my opinion, he identifies the challenges of collecting relevant data throughout the development process (although without mentioning the possibility that the data gathering process might extend into the real life deployment of the SoC into an end product). And I’d certainly agree that another challenge is to process that data to provide engineers with a dashboard view of what’s going on inside their SoCs.