System designers can use UltraSoC’s SoC monitoring and analytics features to refine performance based on the in-silicon behavior of their SoCs.
All-to-often, the real-world performance seen when first silicon arrives from the fab does not meet the full expectations of the silicon architect. Perhaps the chip is functionally free from bugs, but cannot attain the maximum designed-for data rate; or it may “run a little hot” – the power consumption figures are within the design limits, but higher than the ideal.
UltraSoC can help in this situation. By integrating fit-for-purpose non-intrusive monitoring and profiling blocks into the hardware design, the engineering team can obtain actionable intelligence from the real silicon, that they can use to tune performance parameters. For example, such information might show that it is possible to slow down or turn off a particular functional block without impacting performance.
We also assist the software team, who get to see logic-analyzer-like traces created by their software running on real silicon – a prime opportunity to refine and produce better code.
Making design decisions based on real data can help during the silicon bring up and post-silicon validation phases. And it can help the architecture team as they start work on the next generation of devices, providing known-good input for simulations, and guiding the team towards promising avenues for performance enhancement, power saving and cost reduction / value engineering.
UltraSoC plays an active role in a number of initiatives related to systems optimization, and in particular energy consumption. The spEEDO program, in collaboration with the University of Cambridge Computer Laboratory, has already yielded results, presented in 2015 in a paper entitled “Fine-grained Energy/Power Instrumentation for Software-level Efficiency Optimization“.
We are also a member of PRiME, a £5.6m, five-year research programme (2013-2018) funded by the UK’s Engineering and Physical Sciences Research Council (EPSRC). PRiME’s objective is to enable processor core scaling with sustainable energy consumption and reliability. You can read more about the program here.